BCD Audio press announcement
London, 5th October 2015
21st Century Audio links - introducing 20S4
20S4 – what is it for?
24bit audio links were invented in the early days of digital audio, when DSP was 24bit, and converters 20bit. Today, processors are 32bit or better, but we continue to interconnect them with 24bit links, meaning that loud signals are clipped at the interface, and quiet signals suffer from quantisation distortion. Its a bit like having an analogue mixer with +/-48V power rails, except that the output stages are powered from +/6V! Modern converters are still close to 20bit, although a 32bit generation is starting to appear.
24bit PCM is perfectly good for controlled sound, so 20S4 is not intended to replace programme distribution systems at all. It should however find application in point-point links between say a stage box and an audio mixer, or a studio wall box and a mixer, where the added 48dB overload margin will eliminate digital clip before a main fader.
20S4 – in brief
20S4 is a version of floating point, that can fit in 24bits, so can be transported by 24bit links.
Its 20bit linear part ensures the audio distortion is better than the best analogue, and a 4bit scale factor gives 216dB dynamic range, which is equivalent to 32bit linear. There is no added latency.
Why not use Single Precision Floating point?
Single precision Floating point requires 32bits as a minimum, so cannot be passed down 24bit pathways. AOIP is currently set up for 24bit signals, and changing to 32bit would add 25% more bandwidth. AES3 , MADI and Embedded audio are defined as 24bit.
What about compatibility issues?
20S4 is proposed for dedicated point-point links, where compatibility is not an issue.
However 'non-audio' on AES3 has been accepted for decades, and is used for Dolby streams , where the 'non-audio' flag is asserted. This flag, present in AES3 should mute any AES3 receivers that conform to the existing standards. A 20S4 stream should assert 'non-audio'.
A 20S4 encoder is simple to implement in FPGAs or DSPs, and can be switched between 24bit PCM and 20S4. In PCM mode loud signals will clip at 0dBFS. In 20S4 mode, the signal will not clip until +48dBFS.
A 20S4 decoder is simple to implement in FPGAs or DSPs. The decoder can be switched between 24bit and 20S4, takes in 24bit samples and creates 32bit samples.
20S4 / PCM autodetect
An auto-detect module can be added to new designs. The data samples are inspected , and a flag is passed to the decoder, which can now automatically switch to the correct mode, and be taken to the control surface. The auto-detect algorithm is tolerant to sustained clipped PCM signals, and can recognise low level or muted 20S4 signals. A new design could mute automatically if it did not support 20S4.
What is the alternative?
The stage-box to mixer application could definitely benefit from a link better than the existing 24bit. There are proposals to combine two 24bit samples together, for added resolution, This could either be done as left with right pairs ( double the number of channels required ) or at double sample rate pairs ( All paths now need to support the double rates ). 20S4 avoids these issues.
AOIP could support better resolution links, but has added latency compared to AES3 or MADI.